Many problems in microprocessor design arise with the increasing operational speed, of the microprocessor. For example, synchronizing signals crossing different chips is a big issue to be solved.
Please refer to FIG. 1A, in which a chip scheme consisting of three chips is exemplified. The signals crossing the chips are illustrated in FIG. 1B. The way for the third chip C3 to receive a cross-chip signal from the first chip C1 can be a direct path from the first chip C1 or a path through the second chip C2. That is, the first chip C1 directly transmits a cross-chip signal CS3 to the third chip C3, or the first chip C1 transmits a first cross-chip signal CS1 to the second chip C2, and then the second chip C2 transmits a second cross-chip signal CS2 to the third chip C3. It is assumed that the cross-chip signal CS2 is transmitted to the third chip C3 after a time period t13. Generally, it is required that the cross-chip signal CS2 has to synchronize the cross-chip signal CS3 or be kept a constant phase difference t23 from the cross-chip signal CS3 as shown in FIG. 1B.
In prior art, a delay cell (not shown) is used to generate a delay signal DS to the first chip C1 to result in a constant delay period t12 of the cross-chip signal CS3, thereby maintaining the desired phase difference of t23 between the cross-chip signals CS2 and CS3. However, the cross-chip signal CS2 is generated after the transmission of the cross-chip signal S1 from the first chip C1 to the second chip C2, and it is difficult in practice to determine the accurate time for the cross-chip signal CS2 to reach the third chip C3. Many uncertain factors have to be taken into considerations. The uncertain factors include pad delay, PCB (printed circuit board) delay, and any other factors resulting from manufacturing processes or layout. The constant delay of the delay cell cannot flexibly follow the possible change of the actual time for the cross-chip signal CS2 to reach the third chip C3 due to the uncertain factors, particularly arising for the manufacturing processes or layout. Accordingly, the desired constant phase difference t23 between the cross-chip signals CS2 and CS3 cannot be assured of. In a high-frequency system, the misaligning problem is even significant. As is understood, the acceptable deviation is relatively low in a high-frequency system. The inaccurate phase difference t23 between the cross-chip signals CS2 and CS3 is subject to the error function of the third chip C3.